There are two types of firmware in the Micro1401 Mk 2: software and hardware. The software firmware is the program code that tests the Micro1401 when you switch it on and that then obeys instructions transmitted from the host. The hardware firmware includes controls for components such as the ADC and DACs, the clocks, the digital input and output, and the host ports.
| Date |
Revision |
Summary |
| 12/09 |
16 |
| CEDpost |
14 |
Self Test |
| Pld851 |
13 |
FPGA |
| M1401 |
14 |
Monitor |
| Angel |
02 |
Boot |
- Fixes a rare DAC write timing error present in Pld851 versions 11 and 12
|
| 01/09 |
15 |
| CEDpost |
14 |
Self Test |
| Pld851 |
12 |
FPGA |
| M1401 |
14 |
Monitor |
| Angel |
02 |
Boot |
- Self-test code adjusted to avoid very rare false errors.
- Added hardware to detect source of overrun errors.
- Corrected fault in triggered ADC clock start in Pld851 version 11.
- Fixed timing error at start of clocked ADC conversions.
|
| 10/08 |
14 |
| CEDpost |
13 |
Self Test |
| Pld851 |
10 |
FPGA |
| M1401 |
14 |
Monitor |
| Angel |
02 |
Boot |
- Many tests protected against pulses on event inputs during tests.
- Added extra test for clocked ADC conversions.
- Added support for OVRSRC register to give more information in the event of an interrupt error.
- Code emulating EEPROMs in flash memory improved to avoid problems with EEPROM writes.
|
| 04/08 |
13 |
| CEDpost |
12 |
Self Test |
| Pld851 |
10 |
FPGA |
| M1401 |
13 |
Monitor |
| Angel |
02 |
Boot |
- Correction to the host transfer code to fix a problem with the new high-efficiency data transfers in Spike2.
|
| 04/08 |
12 |
| CEDpost |
12 |
Self Test |
| Pld851 |
10 |
FPGA |
| M1401 |
12 |
Monitor |
| Angel |
02 |
Boot |
- Provides scatter/gather data transfer mechanisms for transfers to host PC, plus generalised I2C bus access functions.
|
| 10/07 |
11 |
| CEDpost |
12 |
Self Test |
| Pld851 |
10 |
FPGA |
| M1401 |
11 |
Monitor |
| Angel |
02 |
Boot |
- SetADCList extended to allow sub-bursts.
- Uses EEPROM tag to detect sync hardware.
|
| 11/06 |
10 |
| CEDpost |
12 |
Self Test |
| Pld851 |
10 |
FPGA |
| M1401 |
10 |
Monitor |
| Angel |
02 |
Boot |
- Self test does not generate spurious E0CSR and E1CSR reset test errors when signals are connected to E0 and E1 inputs.
|
| 05/06 |
9 |
| CEDpost |
11 |
Self Test |
| Pld851 |
10 |
FPGA |
| M1401 |
10 |
Monitor |
| Angel |
02 |
Boot |
- USB data handling in high-load situations improved
- ADC overrun interrupt test timing improved, interrupt test checks for no interrupt
- Waits for the USB interface to be configured before starting self-test
- Enhanced reset pulse generation and system timer interrupt handling
|
| 02/05 |
8 |
| CEDpost |
09 |
Self Test |
| Pld851 |
08 |
FPGA |
| M1401 |
09 |
Monitor |
| Angel |
02 |
Boot |
- SetTimerClock supports T clock character to select edge-triggered start in e.g. DIGTIM.
- Self-test handles error LED better when reporting errors via the USB interface.
|
| 08/04 |
7 |
| CEDpost |
08 |
Self Test |
| Pld851 |
08 |
FPGA |
| M1401 |
08 |
Monitor |
| Angel |
02 |
Boot |
- INFO and CONFIG commands extended
|
| 04/04 |
6 |
| CEDpost |
08 |
Self Test |
| Pld851 |
08 |
FPGA |
| M1401 |
07 |
Monitor |
| Angel |
02 |
Boot |
- USB reset logic improved
- ADC multiplexer bit 6 and test register implemented
- Improved tests on clocked digital outputs
- Improved USB support
- Improved USB type detection
- Extended INFO command
|
| 04/03 |
5 |
| CEDpost |
06 |
Self Test |
| Pld851 |
07 |
FPGA |
| M1401 |
05 |
Monitor |
| Angel |
02 |
Boot |
- Prevents USB character data overflow
- Better timing in topbox serial EEPROM access
- Fixed debug ramp address and ramp data loops
|
| 10/02 |
4 |
| CEDpost |
06 |
Self Test |
| Pld851 |
07 |
FPGA |
| M1401 |
04 |
Monitor |
| Angel |
02 |
Boot |
- Self test Post now tests the DILDATN logic
- FPGA Pld has improved DAC update timing
|
| 08/02 |
3 |
| CEDpost |
04 |
Self Test |
| Pld851 |
06 |
FPGA |
| M1401 |
04 |
Monitor |
| Angel |
02 |
Boot |
- Self test: Added support for 2270 chip and top box test registers.
- FPGA: Improved timing for USB interface access, added non-destructive read address (DILDATN) for digital input data low byte.
- Monitor: Added support for 2270 chip, and large numbers of ADC channels. Flash slot erase command added.
- Boot: Added initialisation code for 2270.
|
| 03/02 |
2 |
| CEDpost |
02 |
Self Test |
| Pld851 |
01 |
FPGA |
| M1401 |
03 |
Monitor |
- Self-test: Adjusted to handle both 10 volt build and Patch option in DAC tests.
- Monitor: Fixed possible timing problem with very fast host PCs
|
| 12/01 |
1 |
| CEDpost |
01 |
Self Test |
| Pld851 |
01 |
FPGA |
| M1401 |
02 |
Monitor |
- The command loading was made more robust.
|