Recent technical history of Power1401 mk 1 firmware

Latest version freely down-loadable now. If your serial number is above P4000, see the history of the Power1401 mk 2.

There are two types of firmware in the Power1401: software and hardware. The software firmware is the program code that tests the Power1401 when you switch it on and that then obeys instructions transmitted from the host. The hardware firmware includes controls for components such as the ADC and DACs, the clocks, the digital input and output, and the host ports.

Date Revision Summary
04/08 19
CEDpost 0.29 Power up Self Test
MonitorR 34 Monitor
Pld711 20 Analogue (ANAFPGA)
Pld701 17 Digital (DIGFPGA)
Ang285 04 Boot
  • Correction to the host transfer code to fix a problem with the new high-efficiency data transfers in Spike2.
04/08 18
CEDpost 0.29 Power up Self Test
MonitorR 33 Monitor
Pld711 20 Analogue (ANAFPGA)
Pld701 17 Digital (DIGFPGA)
Ang285 04 Boot
  • Provides scatter/gather data transfer mechanisms for transfers to host PC.
  • Made much more resistant to external event pulses during self-test, which previously could hang a Power1401.
10/07 17
CEDpost 0.28 Power up Self Test
MonitorR 32 Monitor
Pld711 20 Analogue (ANAFPGA)
Pld701 17 Digital (DIGFPGA)
Ang285 04 Boot
  • SetADCList extended to allow sub-bursts.
  • Avoids silly behavior of gain command with non-existent ADC channels.
  • Uses EEPROM tag to detect sync hardware.
11/06 16
CEDpost 0.28 Power up Self Test
MonitorR 31 Monitor
Pld711 20 Analogue (ANAFPGA)
Pld701 17 Digital (DIGFPGA)
Ang285 04 Boot
  • Waits for USB interface to be configured before starting self-test to avoid spurious errors.
  • Self test does not generate spurious E0CSR and E1CSR reset test errors when signals are connected to E0 and E1 inputs.
06/06 15
CEDpost 0.26 Power up Self Test
MonitorR 31 Monitor
Pld711 20 Analogue (ANAFPGA)
Pld701 17 Digital (DIGFPGA)
Ang285 04 Boot
  • USB data handling in high-load situations improved.
12/04 14
CEDpost 0.26 Power up Self Test
MonitorR 30 Monitor
Pld711 20 Analogue (ANAFPGA)
Pld701 17 Digital (DIGFPGA)
Ang285 04 Boot
  • Handles Error LED better with USB.
  • Added ADC channel simulation.
  • Internal FlushCache procedure corrected.
07/04 13
CEDpost 0.25 Power up Self Test
MonitorR 29 Monitor
Pld711 20 Analogue (ANAFPGA)
Pld701 17 Digital (DIGFPGA)
Ang285 04 Boot
  • Fixed delay ramps with standard host port, extensions to INFO and CONFIG commands.
01/04 12
CEDpost 0.25 Power up Self Test
MonitorR 27 Monitor
Pld711 20 Analogue (ANAFPGA)
Pld701 17 Digital (DIGFPGA)
Ang285 04 Boot
  • POST supports issue E PCB including USB2 interface, improved ADC hardware tests, handles large memories better, and has better USB hardware detection.
  • Monitor supports issue E PCB including USB2 interface, improved USB hardware detection, INFO command extended.
  • Pld supports issue E PCB including USB2 interface, improved timings throughout.
10/03 11
CEDpost 0.20 Power up Self Test
MonitorR 24 Monitor
Pld711 19 Analogue (ANAFPGA)
Pld701 15 Digital (DIGFPGA)
Ang285 04 Boot
  • Boot gives better initialisation on startup.
  • POST tests clocked digital outputs and ADC overrun interrupt.
  • DAC LEDs behave correctly, supports event polarity topbox tag.
  • Improved reset behaviour with USB.
  • Enhanced ADC control.
04/03 10
CEDpost 0.18 Power up Self Test
MonitorR 23 Monitor
Pld711 16 Analogue (ANAFPGA)
Pld701 12 Digital (DIGFPGA)
  • Prevents USB character data overflow.
  • Better timing in topbox serial EEPROM access.
  • ParseADCList works with special test channels.
  • CONFIG command supports synchronisation.
  • PGF topbox support added, GAIN command fixed.
10/02 9
CEDpost 0.18 Power up Self Test
MonitorR 22 Monitor
Pld711 16 Analogue (ANAFPGA)
Pld701 12 Digital (DIGFPGA)
  • Self test Post now tests the DILDATN logic.
  • DIGFPGA: added non-destructive read address (DILDATN) for digital input data low byte.
  • Avoids spurious errors with multiple top boxes.
07/02 8
CEDpost 0.17 Power up Self Test
MonitorR 22 Monitor
Pld711 16 Analogue (ANAFPGA)
Pld701 10 Digital (DIGFPGA)
  • Avoids spurious errors with multiple top boxes
03/02 7
CEDpost 0.16 Power up Self Test
MonitorR 22 Monitor
Pld711 16 Analogue (ANAFPGA)
Pld701 10 Digital (DIGFPGA)
  • Monitor: Fixed timing problem with very fast host PCs that might cause data transfers to hang
  • Self-test: Error levels in ADC noise test adjusted
02/02 6
CEDpost 0.15 Power up Self Test
MonitorR 21 Monitor
Pld711 16 Analogue (ANAFPGA)
Pld701 10 Digital (DIGFPGA)
  • Support for the Power1401 Signal top-box 2701-5 added
  • Self-test when there is no USB cable improved
07/01 5
CEDpost 0.14 Power up Self Test
MonitorR 20 Monitor
Pld711 16 Analogue (ANAFPGA)
Pld701 10 Digital (DIGFPGA)
  • Allows use of the maximum possible number of ADC channels
05/01 4
CEDpost 0.14 Power up Self Test
MonitorR 19 Monitor
Pld711 16 Analogue (ANAFPGA)
Pld701 10 Digital (DIGFPGA)
  • Default event polarity is now falling
  • ±10V units now detected correctly
  • Extra support for 1 ADC channel @ 2.5 MHz
  • Added support for PGA 16 top box
09/00 3
CEDpost 0.10 Power up Self Test
MonitorR 15 Monitor
Pld711 12 Analogue (ANAFPGA)
Pld701 10 Digital (DIGFPGA)
  • Power up self-test improved
  • External clock input operation improved
08/00 2
CEDpost 0.09 Power up Self Test
MonitorR 15 Monitor
Pld711 12 Analogue (ANAFPGA)
Pld701 9 Digital (DIGFPGA)
  • Top box support added
  • USB operation on start-up improved
  • ADC cross-talk test improved
06/00 1
CEDpost 0.06 Power up Self Test
MonitorR 13 Monitor
Pld711 10 Analogue (ANAFPGA)
Pld701 9 Digital (DIGFPGA)
  • Self-test was speeded up and a few spurious errors removed.
  • The ADC command timing and the ADC behaviour were improved.
  • We fixed a problem with the PC quad rate card (1401-50) and we added USB support. USB hardware is present from serial number P2001.
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