Recent technical history of Power1401 mk 2 firmware

Latest version freely down-loadable now. If your serial number is below P4000, see the history of the Power1401 mk 1.

There are two types of firmware in the Power1401: software and hardware. The software firmware is the program code that tests the Power1401 when you switch it on and that then obeys instructions transmitted from the host. The hardware firmware includes controls for components such as the ADC and DACs, the clocks, the digital input and output, and the host ports.

Date Revision Summary
03/10 9
Monitor 8
FPGA 9
  • Experimental cache locking added plus floating-point support. Loaded commands are aligned to a cache line (32-byte) boundary.
  • Fixed problem with DAC FIFO scheme - DAC outputs could freeze up.
11/09 8
Monitor 7
FPGA 8
  • FPGA data is only loaded if not already loaded.
  • The USB code has been rewritten to use 4 endpoint interface with idle watchdog code.
  • DAC silo support and test code added.
10/09 7
Monitor 6
FPGA 8
  • Added support for DAC Silo scheme (not yet supported by software).
  • Changes to overcome Issue C board problems.
10/08 6
Monitor 6
FPGA 6
  • Behaviour of clock 4 flag corrected.
  • 100 ns pulses for digital I/O generated correctly.
  • Code emulating EEPROMs in flash memory improved to avoid problems with EEPROM writes.
  • Cache flush function adjusted to avoid possible MEMDAC problems if interrupts running.
  • I2C bus access functions added to symbol table for access by commands.
  • 1-wire interface functions written and added to symbol table.
  • Extended self-test code for clocked ADC conversions.
06/08 5
Monitor 5
FPGA 5
  • Clock timing tightened to avoid spurious overrun errors.
  • OVRSRC register added.
04/08 4
Monitor 5
FPGA 4
  • Gives better information if an interrupt overrun occurs.
04/08 3
Monitor 4
FPGA 4
  • Provides scatter/gather data transfer mechanisms for transfers to host PC.
  • More resistant to external event pulses during self-test.
11/07 2
Monitor 3
FPGA 4
  • Changes made for 8-bit DAC writes
10/07 1
Monitor 3
FPGA 3
  • SetADCList extended to support sub-bursts.
  • Slightly relaxed analogue self-test limits. Optionally does software clear before reset tests. Error LED operations corrected. Clear flash memory slot n code added.
  • Improved timing for HSS interface so as to work on Test-Rack. Fixed addressing problem for systems with more than 1 top-box.