The input high byte can be programmed for detection and timing of change of state (i.e. any bit changing in either direction). Digital output can be gated with clock 2 so that it updates on clock 2 ticks. Digital output is normally permanently enabled, but either byte may be turned tristate-off by software. It can also be controlled by pin 11 of the output socket. If pin 11 is grounded, both bytes are disabled, i.e. tristate-off ; they are enabled if pin 11 is high or disconnected.
Digital I/O LEDs
Front-panel event-input LEDs flash on detection of active-edge transitions. The quiescent state is set by software command. Front-panel digital-output LEDs simply reflect the state of the bits, being lit whenever their bit is set (high).
Technical details
Front-panel digital I/O is routed through common-mode ferrite chokes to prevent radiation of EMI. Outputs are buffered through 74ACT374s, which can source or sink 24mA.
Unconnected digital inputs read 1, being pulled internally to +5V by 4k7 (rear panel) or 100k (front panel) . Input voltages of more than 2.0V will always read as a logic 1. To appear as logic 0, the input must be pulled down to below 0.8V for at least 1microSec, which takes approximately 1mA (rear), 50microA (front).